A power supply voltage monitor circuit, including an UVLO (under voltage lock out function), can prevent an internal circuit of an IC from performing an abnormal operation, in a case where the power supply voltage drops to or below a level above which the internal circuit can operate. Specifically, a power supply voltage monitor circuit monitors a constant voltage circuit inside an IC. When a power supply voltage Vcc is equal to or lower than the output of the constant voltage circuit, the power supply voltage monitor circuit locks out the operation of the constant voltage circuit. On the other hand, when the power supply voltage Vcc is equal to or higher than the output of the constant voltage circuit, the power supply voltage monitor circuit cancels UVLO and allows the constant voltage circuit to operate normally.
FIG. 5 is one example of such a conventional power supply voltage monitor circuit. A constant voltage Vref outputted from a constant voltage circuit 1 undergoes resistive division by means of resistors R1 and R2 and becomes a voltage V1 at a node a between the resistors R1 and R2. Meanwhile, a power supply voltage Vcc undergoes resistive division by means of resistors R3 and R4 and becomes a voltage V2 at a node b between the resistors R3 and R4. Through a comparison between these voltages V1 and V2, a comparator 2 outputs an output signal Vo indicating the detection of a decrease in the power supply voltage Vcc to thereby output an RST signal, which is a digital signal.
The above-described conventional power supply voltage monitor circuit has the following problem. FIG. 6A shows the rise characteristics of the voltages V1 and V2 in a case of increasing the power supply voltage Vcc from 0 V. FIG. 6B shows a timing chart of the RST signal in the same case. As shown in FIG. 6A, the voltage V2 shows an increase substantially proportional to the increase of the power supply voltage Vcc. On the other hand, due to an influence of the voltage characteristics of n transistors provided to the constant voltage circuit 1, the voltage V1 starts to increase when the power supply voltage Vcc becomes n (n is an integer) times as large as a base-emitter voltage Vbe (point A). Thus, in the case of increasing the power supply voltage Vcc from 0 V, the voltage V1 exceeds the voltage V2 (point B) before the voltage V1 becomes stable (point C). This causes an erroneous output of the RST signal during a time from the point A to the point B. Causing such an erroneous output leads to erroneous execution of the UVLO function by the power supply voltage monitor circuit. As a result, the operation of the whole system becomes unstable.
In this regard, it is possible to control the output signal of the comparator 2 by detecting the point C at which the voltage V1 becomes stable. However, the constant voltage circuit 1 varies from one product to another due to fabrication variations, and it is therefore difficult to accurately figure out the point C at which the voltage V1 becomes stable.